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sourced from the load through the MOSFET.
Depending on the output impedance of the system
and the parasitic inductance, the reverse current in
the MOSFET may exceed the source pulsed current
rating (150A) just before the PI2127 MOSFET is
turned off.
The peak current during an input short condition is
calculated as follows, assuming that the output has
very low impedance and it is not a limiting factor:
The PI2127 internal MOSFET power dissipation can
be calculated with the following equation:
Pd MOSFET = Is 2 ? R DS ( on )
Where:
Is : Source Current
Pd MOSFET : MOSFET power dissipation
R DS(on) : MOSFET on-state resistance
Note: For the worst case condition, calculate with
I PEAK
=
V S * t RVS
L PARASITIC
maximum rated R DS(on) at the MOSFET maximum
operating junction temperature because R DS(on) is
temperature dependent. Refer to Figure 11 for
Where:
I PEAK :
V S :
Peak current in PI2127 MOSFET before it is
turned off.
Input voltage or load voltage at S pin before
normalized R DS(on) values over temperature. The
PI2127 maximum R DS(on) at 25°C is 11m ? and will
increase by 43% at 125°C junction temperature.
The Junction Temperature rise is a function of power
input short condition did occur.
t RVS : Reverse fault to MOSFET turn-off time.
L PARASITIC :Circuit parasitic inductance
dissipation and thermal resistance.
Trise = R θ JA ? Pd MOSFET = R θ JA ? Is 2 ? R DS ( on )
The high peak current during an input short and
before the MOSFET turns off, stores energy in the
circuit parasitic inductance, and as soon as the
MOSFET turns off, the stored energy will be released
Where:
R θ JA :
Junction-to-Ambient thermal resistance
(45°C/Watt)
and this will produce a high negative voltage and
ringing at the MOSFET source. At the same time the
energy stored at the drain side of the internal
MOSFET will be released and produce a voltage
higher than the load voltage. This event will create a
high voltage difference between the drain and source
of the MOSFET. The MOSFET will avalanche, but
this avalanche will not affect the MOSFET
performance because the PI2127 has a fast
response time to the input fault condition and the
stored energy will be well below the MOSFET
avalanche capability .
MOSFET avalanche during input short is calculated
as follows:
This may require iteration to get to the final junction
temperature. Figure 13 and Figure 16 show the
PI2127 internal MOSFET final junction temperature
curves versus conducted current at maximum R DS(on) ,
given ambient temperatures and air flow.
Fault Circuit:
FT is an open collector pin and should be pulled up
to the logic voltage via a resistor (10K ? ).
An internal level shift circuit is implemented to change
the PI2127 controller fault output reference from the
PG pin voltage level to the GND pin voltage level. The
level shift circuit is biased from the D pin to stay active
when the bias voltage at S pin is not available. In
the event of an input short fault condition, the S pin
1 1 . 3 * BV DSS
E AS =
*
2 1 . 3 * BV DSS ? V S
* L PARASITIC * I PEAK
2
will be pulled low (ground) and the PI2127 control
circuit will lose its bias voltage. If the output voltage is
supplied from a redundant source, then the level
Where:
E AS :
Avalanche energy
shifter stays biased and the FT pin will be pulled low
to indicate that the MOSFET is in the OFF condition.
BV DSS : MOSFET breakdown voltage (60V)
Power dissipation:
In Active ORing circuits the MOSFET is always on in
steady state operation and the power dissipation is
derived from the total source current and the on-state
resistance of the MOSFET.
During start-up and before the output voltage is
established, the FT pin will be floating until the
approximately 4.5V is present at the S pin or at D pin.
Thereafter the FT pin is pulled low and stays low until
the PI2127 controller bias voltage V S-PG increases
above the controller Under-Voltage Threshold (V SUVR )
and no fault conditions are present. Once this
Picor Corporation ? picorpower.com
PI2127
Rev 1.3
Page 12 of 19
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